Fpga Design Engineer
Rediflex AB / Datajobb / Malmö
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Lund,
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hela Sverige We are looking for a FPGA Design Engineer.
Responsibilities:
Responsible for RTL Design and Integration, Top level Synthesis and Implementation of 5G Product based design using Xilinx Ultrascale FPGAs
Responsible for creating Micro architecture system design at the top level with inputs from cross functional teams (HW, SW and Verification)
Developed Clocking scheme and Timing Constraints and also responsible for Backend Timing closure at both Synthesis and Implementation stages
Skills:
Proficient in RTL Logic Synthesis of complex SoC Designs with good understanding of timing optimization concepts and design techniques
Hands on expertise in complete FPGA Design flow: RTL Design, FPGA Synthesis, P&R, Timing closure, Functional verification, Board level Debugging and Validation
Experience in RTL Partitioning of complex SoC Designs using different partition algorithms for efficient logic synthesis using Synopsys ASIC Prototyping Systems HAPS-70 and HAPS-80
Good Experience in CDC checks, Linting and Equivalence checks with strong Knowledge in AMBA Bus Interfaces (AXI, AHB, APB), PCIe Bus Architecture and high speed interfaces(e.g. SERDES, GigE, 10GE)
Publiceringsdatum2020-06-24Så ansöker duSista dag att ansöka är 2020-07-08
AdressRediflex AB
Ingenjörsgatan 22
21568 Malmö
Omfattning Detta är ett heltidsjobb.
Arbetsgivare Rediflex AB (org.nr 559023-3226)
Ingenjörsgatan 22 (
visa karta)
215 68 MALMÖ
Ansökan E-post:
rekha@rediflex.com Jobbnummer 5274699
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