Senior Asic Verification Engineer, System Verilog

Paventia AB / Elkraftsjobb / Ospecificerad arbetsort
2018-07-05
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The project scope is to develop new radio technology for 5G and some new radio based products for 4G.
You will work with functional verification of new ASICs and FPGAs.
The work will be carried out in close cooperation with RTL designers.
The work includes:
Verification planning
Verification specification
Verification environment (creation/adaptation/maintenance).
Test case creation
Usage of uVC 's
Development of uVC 's (if needed)
Usage of reference models (if needed)
Constrained random testing
Creation of Coverage matrix
Writing Verification Reports

Long experience from ASIC verification and test bench development
Good knowledge of System Verilog and VHDL
Experience from working with simulation tools such as Mentor and Cadence
Experience from block level and sub-system level test benches using UVM
Experience with version control systems
English (verbal and writing)

You will work as a consultant at our customers' sites

paventia.se

Publiceringsdatum
2018-07-05

Så ansöker du
Sista dag att ansöka är 2018-08-31
Ange följande referens när du ansöker: Sr ASIC Verification Engineer

Kontakt
Ola Svensson info@paventia.se

Företag
Paventia AB

Adress
Paventia AB
Tellusvägen 5
18163 LIDINGÖ

Kontorsadress
Tellusvägen 5

Jobbnummer
4238892

Observera att sista ansökningsdag har passerat.

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