Asic Verification Engineer

Afss Consultancy Services Sweden Fil / Datajobb / Ospecificerad arbetsort
2018-08-17
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The job involves IP design verification within digital ASIC & FPGA projects.

The work includes:
• Verification planning
• Verification specification
• Verification environment (creation/adaptation/maintenance).
• Verification documentation
• Test case creation
• Usage of uVC 's
• Usage of reference models (if needed)
• Constrained random testing
• Creation of Coverage matrix
• Design documentation
• Design verification (regression + development verification)
• Miscellaneous tasks in connection to the block design
• Etc.

Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.

A successful candidate is an experienced verification engineer with 5 or more years of IP verification experience

Verification shall be done using System Verilog/UVM.

Both written and spoken English skills are required.

Publiceringsdatum
2018-08-17

Så ansöker du
Sista dag att ansöka är 2018-09-04

Företag
Afss Consultancy Services Sweden Fil

Jobbnummer
4295863

Observera att sista ansökningsdag har passerat.

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